Impact of Interconnect Variation on Ultra Low Power Clock System
Keywords:
ultra-low power, H-tree CDN, variability, sub thresholdAbstract
By virtue of high component density and enhanced performance state-of-the-art integrated chips, power density has increased considerably. Increased power consumption deteriorates the performance, endangers the reliability and increases the packaging cost and therefore power consumption has emerged as a forefront design metric. An attempt to reduce the power consumption hampers the overall performance and robustness of the system. All these factors viz power, reliability and performance of a digital synchronous system are significantly influenced by the clock system and therefore design of low power and robust clock system becomes obvious. For moderate and low frequency applications having stringent power budget, sub threshold circuits satisfies the demand of ultra-low power. However, due to exponential V-I characteristics, robust design is a critical concern in sub threshold regime. Furthermore, high component density and increased complexity leads to increased wire density. Therefore, along with the challenges posed by performance degradation and PVT variability of device in sub threshold, there is need to investigate the impact of interconnect variation on clock system performance parameters in this regime. This paper therefore, explores the impact of variation in interconnect parameters in buffered as well as unbuffered CDN of low power clock system.
How to cite this article:
Walunj RA, Kharate GK. Impact of Interconnect Variation on Ultra Low Power Clock System. J Adv Res Power Electro Power Sys 2021; 8(1&2):5-13.
References
R. H. Reuss, “Introduction to special issue on circuit technology for ULP,” in Proc. IEEE, Vol. 98, No. 2, pp. 139–143, Feb. 2010
B. C. Paul, A. Agarwal, K. Roy, “Low-Power Design Techniques for Scaled Technologies,” Elsevier, integration, the VLSI journal 39 (2006) 64–89
B. Zhai, D. Blaauw, D. Sylvester, and D. Flautner, “Theoretical and practical limits on dynamic voltage scaling,” in Design Automation Conf., 2004, pp. 868–873.
B. Calhoun and A. Chandrakasan, “Characterizing and modeling minimum energy operation for subthreshold circuits,” in Int. Symp. on Low Power Electronics and Designs, 2004, pp. 90–95.
S.D.Pableand M. Hasan, “Interconnect Design for Sub-Threshold Circuits,” IEEE transactionson nanotechnology, Vol. 11, No. 3, May 2012
H. Soeleman, K. Roy, B. C. Paul, “Robust Sub-threshold Logic for Ultra-Low Power Operation,” IEEE transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 1, Feb. 2000
B. Calhoun, J. Ryan, S. Khanna, M. Putic, J. Lach, “Flexible Circuits and Architechtures for Ultralow Power,” Proceedings of the IEEE, Vol. 98, No. 2, Feb. 2010
R. Baker, “ CMOS Ciruit Design ,Layout and Simulation ,”Third Edition ,IEEE Press, John Wiley &Sons, Inc. Publication ,2010
A. Wang, B. H. Calhoun,and A. P. Chandrakasan, Sub- Threshold Design forUltra Low-Power Systems,1st ed. New York: Springer 2006
N. Weste and D. Harris, “CMOS VLSI Design A Circuits and Systems. Perspective,” Fourth Edition Addison-Wesley, Pearson Education
E. G. Friedman, “Clock Distribution Networks in Synchronous Digital Integrated Circuits,” Proc. of IEEE, 89(5):665–692, May 2001.
J. Rabey, A. Chandrakasan & B. Nikoloic, “Digital Integrated Circuits- A Design Perspective,” 2nd Edition, Prentice Hall, New Jersey, USA,2003.
J. Reuben, M. Zackriya, V. Harish, M. Shoaib, “A Buffer Placement Algorithm to Overcome Short-Circuit Power Dissipation in Mesh Based Clock Distribution Network,” Engineering Science and Technology an International Journal 18, 135-140 , 2015
G. T´ellez, M. Sarrafzadeh, “Minimal Buffer Insertion in Clock Trees with Skew and Slew Rate Constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 4, April 1997
A. Rajaram, H. Jiang and R. Mahapatra, “Reducing Clock Skew Variability via Cross links,” IEEE Transactions on Computer-Aided of Integrated Circuits and Systems, Vol. 25 ,No. 6.
M. Dave, M. Jain, M. Baghini, D. Sharma, “A Variant Tolerant Current Mode Signalling Scheme for On Chip Interconnects,” IEEE Transactions on Very Large Scale (VLSI) Systems, Vol. 21, No.2, Feb.2013
R. Islam, M. Gauthas, “Low Power Clock Distribution Using A Current Pulsed Clocked Flip-Flop,” IEEE Transactions on Circuits and Systems- I Regular Papers, Vol.62, No. 4, April 2015
A. Abdelhadi, R. Ginosar, A. Kolodny, E. Friedman, “Timing Driven Variation Aware Synthesis of Hybrid Mesh / Tree Clock Distribution Networks,” Integration, the VLSI journal 46, 382–391, 2013
L. Gaioni, F. DeCanio, M. Manghisoni, L. Ratti, V. Re, G. Traversi, “Design and Test of Clock Distribution Circuits for the Macro Pixel ASIC,” Nuclear Instruments and Methods in Physics Research, Elsevier,2015.
V. Tenace, S. Miryala, A. Calimera, A. Macii, E. Macii, M. Poncino, “Row Based Body Bias Assignment for Dynamic Thermal Clock-Skew Compensation,” Microelectronics Journal 45, 530-538, 2014
S. D. Pable and M. Hasan, “High Speed Interconnect Through Device Optimization for Sub-threshold FPGA,” Microelectronics Journal 42, 545–552, 2011.
J. R. Tolbert, X. Zhao, S. K. Lim, S. Mukhopadhyay, “Slew-Aware Clock Tree Design for Reliable Sub-threshold Circuits, ISLPED Aug. 2009.
J. Kil, J. Gu, and C. H. Kim, “A High – Speed Variation – Tolerant Interconnect Technique for Sub-threshold Circuits using Capacitive Boosting,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No.4, pp. 456-465, Apr. 2008.
[online]. Available: /http//www.eas.asu.edu/ptm/S
