Design and Implementation of Novel Design Methodology for Securing the Internet of Things Applications
Keywords:
Register Transfer Level (RTL), FPGA-SOC, Simulation, Synthesis, Placement & Routing and Hardware ValidationAbstract
Typically, in the Internet of Things (IoT) yields objects are controlled and monitored remotely over a network. A standard IoT system includes various sensors that combine with microprocessors and other custom peripherals to perform their operations. Data collection and processing, computation, and finally communication these operations are involved to carry out IoT applications. Designer and user both demand these operations should be performed without any kind of unauthorized interference. As per the current trend, the way we have relied on technology, the way data exchange has started, it is not possible to rely on existing data security systems. It has become imperative to add a concrete solution to the existing infrastructure of security. Hardware security is attracted attention of researchers because of its importance in IoT applications, IP securities, and controlling counterfeit electronic devices. Physically Unclonable Functions (PUF) is an innovative approach that provides security primitives and also will resist Integrated Circuit (IC) cloning and counterfeiting. PUF works on the principle of process variations present inside the hardware. PUFs carry capricious and event-specific values and can be used to provide hardware security. Nowadays IoT design has been implemented on the SoC platform. Here we have designed PUF on the SoC platform so that it will be helpful to IoT designs. The presented work will help in understanding the ROPUF design with respect to simulation, synthesis, placement and routing and hardware validation.
How to cite this article:
Kulkarni S, Vani RM, Hunagund PV. Design and Implementation of Novel Design Methodology
for Securing the Internet of Things Applications. J Engr Desg Anal 2021; 4(2): 6-11.
DOI: https://doi.org/10.24321/2582.5607.202101
References
Alkatheiri MS, Zhuang Y, Korobkov M et al. An experimental study of the state-of-the-art PUFs implemented on FPGAs. in 2017 IEEE Conference on Figure 9.(b) Resource Utilization Figure 10.SDK console Contains the final Input and Output of RO PUF Dependable and Secure Computing, 2017: 174-180.
Choudhury M, Pundir N, Niamat et al. Analysis of a novel stage configurable ROPUF design. in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017: 942-945.
Deng D, Hou S, Wang Z et al. Configurable Ring Oscillator PUF Using Hybrid Logic Gates. IEEE Access 2020; 8:161427-161437.
Halak B, Hu Y, Mispan MS. Area efficient configurable physical unclonable functions for FPGAs identification. 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015; 946-949.
Herder C, Yu M-D, Koushanfar F et al. Physical unclonable functions and applications: A tutorial. Proc. IEEE 2014; 102(8): 1126-1141.
Herder C, Yu M-D, Koushanfar F et al. Physical unclonable functions and applications: A tutorial. Proc. IEEE 2014; 102(8): 1126-1141.
Kodytek F, Lórencz R. A design of ring oscillator based PUF on FPGA. 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015: 37-42.
Kokila J, Ramasubramanian N. Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs. J Electron Test 2019; 35(4): 543-558.
Kulkarni S, Vani RM, Hunagund PV. FPGA based Hardware Security for Edge Devices in Internet of Things. in 2020 5th International Conference on Communication and Electronics Systems (ICCES), 2020: 1133-1138, doi: 10.1109/ICCES48766.2020.9138013.
Mahalat MH, Ugale N, Shahare R et al. Design of latch based configurable ring oscillator puf targeting secure fpga. in 2018 IFIP/ IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018; 261-266.
Maiti A, Casarona J, McHale L et al. A large scale characterization of RO-PUF. IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2010: 94-99.
Maiti A, Schaumont P. Improved ring oscillator PUF: An FPGA-friendly secure primitive. J Cryptol 2011; 24(2): 375-397.
M. Masoumi and A. Dehghan. Design and implementation of a ring oscillator-based physically unclonable function on field programmable gate array to enhance electronic security. Int J Electron Secur Digit Forensics 2020; 12(3): 243-261.
Ning H, Farha F, Ullah A et al. Physical unclonable function: architectures, applications and challenges for dependable security. IET Circuits, Devices & Syst, 2020; 14(4): 407-424.
Patterson M, Zambreno J, Sabotta C et al. Ring oscillator PUF design and results 2011.
Schaub A, Danger J-L, Guilley S et al. An improvedanalysis of reliability and entropy for delay PUFs. 2018 21st Euromicro Conference on Digital System Design (DSD), 2018: 553-560.
Shamsoshoara A, Korenda A, Afghah F. A survey on physical unclonable function (PUF)-based security solutions for Internet of Things. Comput. Networks 2020; 183: 107593.
Sklavos N. Securing communication devices via physical unclonable functions (PUFs),” in ISSE 2013 Securing Electronic Business Processes, Springer, 2013: 253-261.
Suh GE, Devadas S. Physical unclonable functions for device authentication and secret key generation. in 2007 44th ACM/IEEE Design Automation Conference, 2007: 9-14.
Usmani MA, Keshavarz S, Matthews E et al. Efficient PUF-based key generation in FPGAs using per-device configuration. IEEE Trans very large scale Integr Syst 2018; 27(2): 364-375.
Yan W, Chandy J. Phase Calibrated Ring Oscillator PUF Design and Application. Computers 2018; 7(3): 40.
Zhang J-L. Techniques for design and implementation of an FPGA-specific physical unclonable function. J Comput Sci Technol 2016; 31(1): 124-136.
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug835-vivado-tcl-commands.pdf
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug901-vivado-synthesis.pdf
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