Hardware Architecture for Color Image Mosaicing using DCT Approach
Keywords:
CIM-DCT, HDL, RTL, Architecture, HardwareAbstract
It is challenging to implement and develop software-based corner detection on hardware architecture. The proposed Color Image Mosaicing with DCT Approach (CIM-DCT) is presented together with a basic hardware architecture for Verilog implementation. New optimized hardware architecture has been introduced to provide high-performance image processing in hardware while reducing computing complexity using Verilog-HDL and Xilinx 14.7 software, the recommended hardware architecture CIM-DCT was constructed. to target the Artix-7 FPGA device XC7A100T-3CSG324. For simulation of the RTL Verilog codes, ModelSim was used. For a clock rate of 50 MHz, the whole processing of a large image 1600x1200 pixels takes 23040030 ns.
How to cite this article:
Jayalaxmi H, Ramachandran S, Shridhar H. Hardware Architecture for Color Image Mosaicing
using DCT Approach Color Image Mosaicing with a DCT Approach Hardware Architecture. J Engr Desg Anal 2021; 4(2): 12-15.
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