LINE BALANCING TECHNIQUE IMPROVES PRODUCTIVITY AT CHIPSET TESTER ASSEMBLY MANUFACTURING: A REVIEW
Keywords:
Line Balancing Technique, Time Study, Bottleneck, Tester Manufacture, Productivity ImprovementAbstract
This paperreviews line balancing technique that used to for productivity purpose. Globalization is one of the key factors that brought growth in the chipset production demand. As a tester supplier for the chipset world, production capacity is one of the main concern in the chipset tester production. However, one of the biggest challenges that tester manufacture facing in human operated production output unable to meet target productivity as per planning, and production capacity is not fully utilized. Besides, tester manufacture is a Multi Model Assembly Line, which may causing difficulties in the line balancing analysis, Thus, in this review paper, time study methodologies is reviewed, in order to compare the cycle time collection methods and bottleneck identification process. Besides, a line balancing methodologieshave been reviewed, in order to compared the methods of improvement.
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